胡金 專案

Implements a hierarchical 1-to-16 demultiplexer using a 1x2 and two 1x8 demux blocks in Verilog. Directs a single input signal to one of 16 outputs based on select lines. Features: Hierarchical Verilog modules (1x2 and 1x8), Behavioral testbench for all 16 select combinations, Graph-based output verification

Verilog behavioral models of SR, D, JK, and T flip-flops with testbenches and simulation results.

SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.

Verilog implementation of a synchronous 4-bit up/down decade counter with asynchronous clear, load, and carry-out features. Also includes a 2-decade decimal counter design using two such counters cascaded together. Simulates counting up/down from 00 to 99 with load, increment, and clear operations.

SystemVerilog implementations of a 101 pattern detector using both structural and behavioral modeling styles. Includes separate testbenches for each implementation. Designed for detecting overlapping 101 patterns in a serial bitstream, useful for learning FSM design and simulation in digital systems.

Full-stack Driver Scheduling System for managing drivers and delivery routes in a simple, visual way. Built with Node.js and React.js, it provides an intuitive dashboard to add drivers, create routes, and track assignments in real time. Developed for the DRB Internship Program 2025, highlighting clean design and practical scheduling tools.