RISC-V XV6/Linux SoC, marchID: 0x2b
-
Updated
Nov 14, 2025 - Verilog
RISC-V XV6/Linux SoC, marchID: 0x2b
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.
VSDIAT Documentation- Openlane/Sky130- MIT
An open source SoC project for the VLSI 2 class at ETHZ. Selected as one of the best design and taped out in IHP 130nm technology
Add a description, image, and links to the chipdesign topic page so that developers can more easily learn about it.
To associate your repository with the chipdesign topic, visit your repo's landing page and select "manage topics."