Testbenches for i2c in

[Kreijstal]

1. separated phy from master,
2. added 'tb' just for phy
3. formatted everything with verible-verilog-format
4. testing
   rtl/
   -i2c_master.v
   -i2c_slave.v
   -i2c_single_reg.v
   with iverilog and verilator, it works
   verilator -y rtl rtl/i2c_master_tb -main --timing --binary --Wno-style --trace-fst &&./obj_dir/Vi2c_master_tb
iverilog -o sim_output -y rtl rtl/i2c_master_tb.v && ./sim_output

I have no use for axil or wbm