Verilog: KNOWNBUG test for typed parameter ports

Author: kroening

regression/verilog/modules/parameter_ports5.desc

@@ -0,0 +1,7 @@
+KNOWNBUG
+parameter_ports5.v
+
+^EXIT=0$
+^SIGNAL=0$
+--
+The type of the parameter is ignored.

regression/verilog/modules/parameter_ports5.sv

@@ -0,0 +1,12 @@
+module sub #(parameter byte P = 0);
+
+  initial assert($bits(P) == 8);
+  initial assert(P == 2);
+
+endmodule
+
+module main;
+
+  sub #('h102) submodule();
+
+endmodule // main